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LTC1152 Rail-to-Rail Input Rail-to-Rail Output Zero-Drift Op Amp
FEATURES
s s s s s s s s s s s
DESCRIPTIO
Input Common-Mode Range Includes Both Rails Output Swings Rail to Rail Output Will Drive 1k Load No External Components Required Input Offset Voltage: 10V Max Input Offset Drift: 100nV/C Max Minimum CMRR: 115dB Supply Current: 3.0mA Max Shutdown Pin Drops Supply Current to 5A Max Output Configurable to Drive Any Capacitive Load Operates from 2.7V to 14V Total Supply Voltage
The LTC(R)1152 is a high performance, low power zero-drift op amp featuring an input stage that common modes to both power supply rails and an output stage that provides rail-to-rail swing, even into heavy loads. The wide input common-mode range is achieved with a high frequency on-board charge pump. This technique eliminates the crossover distortion and limited CMRR imposed by competing technologies. The LTC1152 is a C-LoadTM of amp, enabling it to drive any capacitive load. The LTC1152 shares the excellent DC performance specs of LTC's other zero-drift amplifiers. Typical offset voltage is 1V and typical offset drift is 10nV/C. CMRR and PSRR are 130dB and 120dB and open-loop gain is 130dB. Input noise voltage is 2VP-P from 0.1Hz to 10Hz. Gain-bandwidth product is 0.7MHz and slew rate is 0.5V/s, all with supply current of 3.0mA max over temperature. The LTC1152 also includes a shutdown feature which drops supply current to 1A and puts the output stage in a high impedance state. The LTC1152 is available in 8-pin PDIP and 8-pin SO packages and uses the standard op amp pinout, allowing it to be a plug-in replacement for many standard op amps.
, LTC and LT are registered trademarks of Linear Technology Corporation. C-Load is trademark of Linear Technology Corporation.
APPLICATI
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S
Rail-to-Rail Amplifiers and Buffers High Resolution Data Acquisition Systems Supply Current Sensing in Either Rail Low Supply Voltage Transducer Amplifiers High Accuracy Instrumentation Single Negative Supply Operation
TYPICAL APPLICATI
Input and Output Waveforms Rail-to-Rail Buffer
5V
5V
IN
+
3
-
2
7 6 OUT
VOUT 2V/DIV 0V 5V VIN 2V/DIV
1152 TA01
LTC1152 4
0V
1152 TA02
U
UO
UO
1
LTC1152 ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW SHDN 1 -IN 2 +IN 3 V- 4 8 7 6 5 CP V+ OUT COMP
Total Supply Voltage (V + to V -) ............................. 14V Input Voltage ............................ V + + 0.3V to V - - 0.3V Output Short-Circuit Duration (Pin 6) ............. Indefinite Operating Temperature Range LTC1152C............................................... 0C to 70C LTC1152I.......................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1152CN8 LTC1152CS8 LTC1152IN8 LTC1152IS8 S8 PART MARKING 1152 1152I
N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 110C, JA = 130C/ W (N8) TJMAX = 110C, JA = 200C/ W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VOS Input Offset Voltage VOS IB IOS en in CMRR PSRR AVOL VOUT Average Input Offset Drift Long-Term Offset Drift Input Bias Current Input Offset Current Input Noise Voltage (Note 3) Input Noise Current Common-Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Maximum Output Voltage Swing (Note 4)
VS = 5V, TA = operating temperature range, unless otherwise specified.
MIN
q
CONDITIONS TA = 25C (Note 1) (Note 1) TA = 25C (Note 2)
q
TYP 1 10 50 10 20
MAX 10 100 100 1000 200 500 3 1
UNITS V nV/C nV/Mo pA pA pA pA VP-P VP-P fA/Hz dB dB dB dB V V V V/s MHz
TA = 25C (Note 2)
q
RS = 100, 0.1Hz to 10Hz RS = 100, 0.1Hz to 1Hz f = 10Hz VCM = 0V to 5V VS = 3V to 12V
q q
2 0.5 0.6 115 110 105 110 4.0 2.0 130 120 130 4.4 2.2 2.49 0.5 0.7
q q q
RL = 10k, VOUT = 0.5V to 4.5V RL = 1k, VS = Single 5V RL = 1k, VS = 2.5V RL = 100k, VS = 2.5V RL = 10k, CL = 50pF, VS = 2.5V RL = 10k, CL = 50pF, VS = 2.5V No Load Shutdown = 0V Shutdown = 0V ICP = 0
q q q
SR GBW IS IOSD VCP VIL VIH IIN fCP fSMPL
Slew Rate Gain-Bandwidth Product Supply Current Output Leakage Current Charge Pump Output Voltage Shutdown Pin Input Low Voltage Shutdown Pin Input High Voltage Shutdown Pin Input Current Internal Charge Pump Frequency Internal Sampling Frequency
2.2 1 10 7.3 2.5 4
3.0 5 100
VSHDN = 0V TA = 25C TA = 25C
q
-1 4.7 2.3
-5
2
U
mA A nA V V V A MHz kHz
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LTC1152
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VOS Input Offset Voltage VOS IB IOS en in CMRR AVOL VOUT SR GBW IS IOSD VCP VIL VIH IIN fCP fSMPL Average Input Offset Drift Input Bias Current Input Offset Current Input Noise Voltage (Note 3) Input Noise Current Common-Mode Rejection Ratio Large-Signal Voltage Gain Maximum Output Voltage Swing (Note 4) Slew Rate Gain-Bandwidth Product Supply Current Output Leakage Current Charge Pump Output Voltage Shutdown Pin Input Low Voltage Shutdown Pin Input High Voltage Shutdown Pin Input Current Internal Charge Pump Frequency Internal Sampling Frequency
VS = 3V, TA = operating temperature range, unless otherwise specified.
MIN
q q
CONDITIONS TA = 25C (Note 1) (Note 1) TA = 25C (Note 2) TA = 25C (Note 2)
q
TYP 1 10 5 10 2 0.75 0.6
MAX 10 100 100 1000 200 500
UNITS V nV/C pA pA pA pA VP-P VP-P fA/Hz dB dB V V V/s MHz
RS = 100, 0.1Hz to 10Hz RS = 100, 0.1Hz to 1Hz f = 10Hz VCM = 0V to 3V RL = 10k, VOUT = 0.5V to 2.5V RL = 1k, VS = Single 3V RL = 100k, VS = 1.5V RL = 10k, CL = 50pF, VS = 1.5V RL = 10k, CL = 50pF, VS = 1.5V No Load Shutdown = 0V Shutdown = 0V ICP = 0
q q q q q q
130 106 2.0 130 2.5 1.48 0.4 0.5 1.8 1 10 4.5 1.2 2.3 2.5 5
mA A nA V V V A MHz kHz
VSHDN = 0V TA = 25C TA = 25C
-1 4.2 2.1
The q denotes specifications which apply over the full operating temperature range. Note 1: These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels during automated testing. Note 2: At T 0C these parameters are guaranteed by design and not tested. Note 3: 0.1Hz to 10Hz noise is specified DC coupled in a 10-sec window; 0.1Hz to 1Hz noise is specified in a 100-sec window with an RC highpass
filter at 0.1Hz. Contact LTC factory for sample tested or 100% tested noise parts. Note 4: All output swing measurements are taken with the load resistor connected from output to ground. For single supply tests, only the positive swing is specified (negative swing will be 0V due to the pull-down effect of the load resistor). For dual supply operation, both positive and negative swing are specified.
3
LTC1152 TYPICAL PERFORMANCE CHARACTERISTICS
Common-Mode Range vs Supply Voltage
8
COMMON-MODE RANGE LIMIT (V)
SUPPLY CURRENT (mA)
4 2 0 -2 -4 -6 -8 1 6 3 4 5 2 POWER SUPPLY VOLTAGE (V) 7
1152 G01
2.5
POWER SUPPLY CURRENT (mA)
6
Output Swing vs Load Resistance
6 TA = 25C 5
OUTPUT SWING (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
VS = SINGLE 5V
30 SINK 20
OPEN-LOOP OUTPUT RESISTANCE ()
4 3 2 1 0 VS = SINGLE 3V VS = 2.5V VS = 1.5V
0.2 0.5
1
2 5 10 20 50 100 200 LOAD RESISTANCE (k)
1152 G04
Charge Pump Voltage vs Supply Voltage
3
CHARGE PUMP VOLTAGE, VCP - V+ (V)
CHARGE PUMP VOLTAGE, VCP - V+ (V)
TA = 25C
2
2
INPUT BIAS CURRENT (pA)
1
0
2
4
12 6 8 10 TOTAL SUPPLY VOLTAGE (V)
4
UW
14
1152 G07
Supply Current vs Supply Voltage
3.0 TA = 25C 1.9 1.8 1.7 1.6 1.5 2.0
Supply Current vs Temperature
VS = 5V
2.0
1.5
1.0
0
2
6 8 10 12 4 TOTAL SUPPLY VOLTAGE (V)
14
1152 G02
1.4 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1152 G03
Output Short-Circuit Current vs Supply Voltage
40 TA = 25C SOURCE 300
Open-Loop Output Resistance vs Supply Voltage
TA = 25C 250
200
10
150
0
2
4
6 8 10 12 TOTAL SUPPLY VOLTAGE (V)
14
1152 G05
100
2
4
6 8 10 12 TOTAL SUPPLY VOLTAGE (V)
14
1152 G06
Charge Pump Voltage vs Load Current
3 TA = 25C VS = 5V
1000
Input Bias Current vs Temperature
VS = 5V
100
1
0
0
20
40 60 80 100 120 140 160 LOAD CURRENT (A)
1152 G08
10 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1152 G09
LTC1152 TYPICAL PERFORMANCE CHARACTERISTICS
Gain and Phase Shift vs Frequency
70 60 50
VOLTAGE GAIN (dB)
COMMON-MODE REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
PHASE
TA = 25C VS = 2.5V PIN 5 = NC
40 30 20 10 0 -10 -20 1k 10k
GAIN
100k 1M FREQUENCY (Hz)
Gain and Phase Shift vs Frequency
70 60 50
VOLTAGE GAIN (dB)
PHASE
VOLTAGE NOISE (nV/Hz)
TA = 25C VS = 2.5V CCOMP = 1000pF
40 30 20 10 0 -10 -20 1k 10k 100k 1M FREQUENCY (Hz) GAIN
(V)
Gain and Phase Shift vs Frequency
60 50 40 VOLTAGE GAIN (dB) 30 20 10 0 -10 -20 -30 -40 0.01 0.1 1 FREQUENCY (kHz) 10
1152 G12
TA = 25C VS = 2.5V CCOMP = 0.1F
PHASE
GAIN
UW
1152 G10
1152 G11
Common-Mode Rejection Ratio vs Frequency
120 100 80
PHASE SHIFT (DEG)
PHASE SHIFT (DEG)
Power Supply Rejection Ratio vs Frequency
80 70 60 50 40 30 20 10 0 -10 10 100 1k 10k FREQUENCY (Hz) 100k 1M
1152 G14
110 100 90 80 70 60 50 40 30 0.1 1 10 100 FREQUENCY (kHz) 1000
1152 G13
TA = 25C VS = 2.5V
TA = 25C
60 40 20 0
-PSRR +PSRR
10M
Voltage Noise vs Frequency
120 100
125 150
0.1Hz to 10Hz Input Noise
2
80 60 40 20 0 -20 -40
1
100 75 50
0
-1
25
-60 10M
0
1
10
100 1k FREQUENCY (Hz)
10k
1152 G15
-2 0 2 6 4 TIME (SEC) 8 10
1152 G18
Small-Signal Transient Response
180 160 140 120 100 80 60 40 20 0 -20 PHASE SHIFT (DEG) VS = 2.5V AV = 1
1152 G16
Large-Signal Transient Response
VS = 2.5V AV = 1
1152 G17
5
LTC1152
APPLICATI
S I FOR ATIO
Rail-to-Rail Operation The LTC1152 is a rail-to-rail input common-mode range, rail-to-rail output swing op amp. Most CMOS op amps, including the entire LTC zero-drift amplifier line, and even a few bipolar op amps, can and do, claim rail-to-rail output swing. One obvious use for such a device is to provide a unity-gain buffer for 0V to 5V signals running from a single 5V power supply. This is not possible with the vast majority of so-called "rail-to-rail" op amps; although the output can swing to both rails, the negative input (which is connected to the output) will exceed the common-mode input range of the device at some point (generally about 1.5V below the positive supply), opening the feedback loop and causing unpredictable and sometimes bizarre behavior. The LTC1152 is an exception to this rule. It features both rail-to-rail output swing and rail-to-rail input commonmode range (CMR); the input CMR actually extends beyond either rail by about 0.3V. This allows unity-gain buffer circuits to operate with any input signal within the power supply rails; input signal swing is limited only by the output stage swing into the load. Additionally, signals occurring at either rail (power supply current sensing, for example) can be amplified without any special circuitry. Internal Charge Pump The LTC1152 achieves its rail-to-rail input CMR by using a charge pump to generate an internal voltage approximately 2V higher than V +. The input stages of the op amp are run from this higher voltage, making signals at V + appear to be 2V below the front end's power supply (Figure 1). The charge pump is contained entirely within the LTC1152; no external components are required. About 100VP-P of residual charge pump switching noise will be present on the output of the LTC1152. This feedthrough is at 4.7MHz, higher than the gain-bandwidth of the LTC1152, and will generally not cause any problems. Very sensitive applications can reduce this feedthrough by connecting a capacitor from the CP pin (pin 8) to V + (pin 7); a 0.1F capacitor will reduce charge pump feedthrough to negligible levels. The LTC1152 includes an internal diode from pin 8 to pin 7 to prevent external parasitic capacitance from lengthening start-up
CP (PIN 8) 0.1F* -IN VCC + 2V INTERNAL CHARGE PUMP
+IN
*OPTIONAL EXTERNAL CAPACITOR TO REDUCE CHARGE PUMP FEEDTHROUGH
Figure 1. LTC1152 Internal Block Diagram
time. This diode can stand short-term peak currents of about 50mA, allowing it to quickly charge external capacitance to ground or V -. Large capacitors (>1F) should not be connected between pin 8 and ground or V - to prevent excessive diode current from flowing at start-up. The LTC1152 can withstand continuous short circuits between pin 8 and V +; however, short circuiting pin 8 to ground or V - will cause large amounts of current to flow through the diode, destroying the LTC1152. Don't do it. Output Drive The LTC1152 features an enhanced output stage that can sink and source 10mA with a single 5V supply while maintaining rail-to-rail output swing under most loading conditions. The output stage can be modeled as a perfect rail-to-rail voltage source with a resistor in series with it; this open-loop output resistance limits the output swing by creating a resistor divider with the output load. The output resistance drops as total power supply voltage increases, as shown in the typical performance curves. It is typically 140 with a single 5V supply, allowing a 4.4V output swing into a 1k resistor with a single 5V supply.
VCC (PIN 7)
LTC1152 OUTPUT DRIVER
Figure 2. LTC1152 Output Resistance Model
6
+
-
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VCC (PIN 7) INPUT OUT OUTPUT RAIL TO RAIL
1152 F01
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ROUT OUT (PIN 6) 140 AT 5V SUPPLY RLOAD
1152 F02
LTC1152
APPLICATI
S I FOR ATIO
Compensation/Bandwidth Limiting The LTC1152 is unity-gain stable with capacitive loads up to 1000pF. Larger capacitive loads can be driven by externally compensating the LTC1152. Adding 1000pF between COMP (pin 5) and OUT (pin 6) allows capacitive loading of up to 1F; 0.1F between pins 5 and 6 allows the LTC1152 to drive infinite capacitive load (Figure 3).
1 2 3 4 V- 1N4148* LTC1152 V+ 8 7 6 5 1N4148* CC OUTPUT
*OPTIONAL DIODES TO PREVENT LATCH-UP WITH CC > 1F
1152 F03
Figure 3. Output Compensation Connection
Large compensation capacitors can also be used to limit the bandwidth of the LTC1152. With 0.1F from pin 5 to pin 6, the LTC1152's gain-bandwidth product is reduced from 700kHz to around 200Hz. Note that compensation capacitors greater than 1F can cause latch-up under severe output fault conditions; this can be prevented by clamping pin 5 to each supply with standard signal diodes, as shown in Figure 3. Shutdown The LTC1152 includes a shutdown pin (pin 1). When this pin is at V +, the LTC1152 operates normally. An internal 1A pull-up keeps the pin high if it is left floating. When pin 1 is pulled low, the part enters shutdown mode; supply current drops to 1A, all internal clocking stops and the output enters a high impedance state. During shutdown the voltage at the CP pin (pin 8) will drop to 0.5V below V +. When pin 1 is brought high again, about 10s will elapse before the charge pump regains full voltage. During this time the LTC1152 will operate normally, but the input CMR may not include V +. Pin 1 is compatible with CMOS logic running from the same supply as the LTC1152. Additionally, the input trip levels allow ground referenced CMOS logic signals to interface directly to pin 1 when the LTC1152
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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is running from 5V or 3V supplies. The internal 1A pull-up also allows pin 1 to interface with open-collector/ open-drain devices or discrete transistors. The high impedance output in shutdown allows several LTC1152s to be connected together as a MUX, with their outputs tied in parallel and the active channel selected by using the shutdown pins. Deselected (shutdown) channels will go to high impedance at the outputs, preventing them from fighting with the active channel. This works best when the individual LTC1152s are connected in noninverting feedback configurations to prevent the feedback resistors from passing signals through deselected channels. See the Typical Applications section for a circuit example. Zero-Drift Operation The LTC1152 is a zero-drift op amp. Like other LTC zerodrift op amps, it features virtually error-free DC performance, very little drift over time and temperature, and very low noise at low frequencies. The internal nulling clock runs at about 2.3kHz (the charge pump frequency of 4.7MHz divided by 2048) and is synchronized to the internal charge pump to prevent beat frequencies from appearing at the output. The self-nulling circuit constantly corrects the input offset voltage, keeping it typically below 1V over the entire input common-mode range. This has the added benefit of providing exceptional CMRR and PSRR at low frequencies--far better than competing railto-rail op amps. Because it uses a sampling front end, the LTC1152 will exhibit aliasing behavior and clock noise at frequencies near the internal 2.3kHz sampling frequency. The LTC1152 includes an internal anti-aliasing circuit to keep these error terms to a minimum. As a rule, alias frequencies will be down by (80dB - ACLG) in most standard amplifier configurations, where ACLG is the closed-loop gain of the LTC1152 circuit. Clock noise is also dependent on closedloop gain; it will generally consist of spikes of about 100V in amplitude, input referred. In general, these error terms are too small to affect most applications. For a more detailed explanation of zero-drift amplifier behavior, see the LTC1051/LTC1053 data sheet.
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LTC1152
APPLICATI
S I FOR ATIO
100k 1.5V
High Gain Amplifier with 1.5V Supplies
10
2
- +
7 6 0.1F OUT AV = 10k = 80dB -1.5V
IN 1 AV = 10 10
1152 TA03
LTC1152 IN 3 4
High-Side Power Supply Current Sensing
0.01 5V 0.1F CHANGE SENSE RESISTOR TO CHANGE SENSITIVITY TO MEASURED CIRCUIT
IN 2 AV = 1000
3
+
LTC1152 6
10k
10k
IN 3 AV = 1 3
100
2
-
10k
2
-
LT1097 6
100k 3 10k GND
+
PACKAGE DESCRIPTION
N8 Package 8-Lead Plastic DIP
0.400* (10.160) MAX 8 7 6 5
Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic SOIC
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm). 1 0.300 - 0.325 (7.620 - 8.255) 2 3 4
0.255 0.015* (6.477 0.381)
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.018 0.003 (0.457 0.076) 0.015 (0.380) MIN
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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High Precision Three-Input MUX
1.1k 10k SEL1 2
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- +
10k
1 6
LTC1152 3
OUT SEL2 1 6
2
- +
LTC1152 3
SEL3 2
- +
1 6
LTC1152
OUT 1V/100mA LOAD CURRENT IN MEASURED CIRCUIT 0.1F GND
1152 TA05
SELECT INPUTS ARE CMOS LOGIC COMPATIBLE. SELECT ONLY ONE CHANNEL AT ONCE! 1152 TA04
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157* (3.810 - 3.988)
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
1 0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP
2
3
4 0.004 - 0.010 (0.101 - 0.254)
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
SO8 0294
N8 0694
LT/GP 0195 10K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1995

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